NDL's R&D efforts are mainly associated with Si-based semiconductor devices and materials with a special focus on fabrication and characterization of nano-scale devices. To accomplish this goal, the following modules have been established:

1. Optical and electron-beam lithography.
2. Etching and chemical cleaning.
3. Doping and annealing.
4. Thin film deposition.
5. Process and device simulation.
6. Material characterization.
7. RF device testing and modeling.

Listed below are the names of NDL's research scientists and their current research activities. Please feel free to contact with them for details of their research:

1. Development and application of new materials
2. Development and application of organic films
3. Development of plasma etching technique
   
   

1. Cu CMP technology development
2. Metal slurry research
3. Low k material research
4. Multi-level interconnection development and research

1. Nano device / single electron transistor

1. CMOS/BiCMOS RFIC technology
2. Characterization and modeling of high frequency
3. Modeling of deep sub-µmdevices
4. RFIC/MMIC testing technique

1. Development of lithographic technique
2. Resist characterization
3. Lithographic simulation
4. Development of analytical method for lithographic material

1. Semiconductor nanostructures and physics
2. Development and applications of TCAD for semiconductor process and nanodevices
3. Mathematical modeling, numerial methods, and parallel computation

1. Plasma process-induced damage
2. Reliability of ultra-thin oxides
3. Nano-scale device and process technologies
4. Thin film transistors
5. SOI device

1. Integration of low-k dielectrics and copper interconnect.
2. Study on metallic barriers
3. Mutil-level interconnect technology

1. Fabrication, characterization and application of nanoparticles.
2. Development of biosensor

1. Materials characterization for microelectronics
2. Ultra-trace elemental analysis for the Si wafer surface
3. Ultra-Shallow junction characterization
4. Two dimensional dopant diffusion
5. Interface analysis for interconnects
6. Ultra-cleaning for the silicon surface

1. Low-K material :a-C:F grown by PECVD or HDPCVD with K<2.5 6-inches
2. Cooper electroplating system fulfilling below 0.2um trench or via process phase
3. Shift mask with OPC

1. Development of low-k dielectrics
2. Multilevel interconnect technique
3. Study on Micro-Electromechanical Systems (MEMS)

1. Chemical-mechanical polishing & post-CMP cleaning process
2. Electroless Cu plating
3. Low-k dielectric thin film process
4. Study on electrochemical metal corrosion

1. 2-Dimensional dopant profiles by TEM and SCM
2. Combination of semiconductor processes and electrochemistry
3. Development of low k materials and field emission devices

1. Conductor systems in Cu and Al metallization
2. Silicidation (CoSi₂, NiSi) process
3. Reliability (EM) in metallization
4. Integration of Cu and low-k

1. Thin film fabrication
2. Facilities engineering

1. Development of plasma etching techniques
2. Study on strippers for wet cleaning process