組別：奈米CMOS元件平台組

姓名：賀大偉

職稱：副研究員

學歷：

• Ph. D.: Electrical and Computer Engineering, University of Maryland

經歷：

• Postdoc, SEMACHTECH
• Research Engineer, SEMATECH
• 現為國家奈米元件實驗室副研究員

研究與技術專長：

• 元件模擬
• 元件可靠性量測技術研發
• 元件可靠性機制
• 元件物理

個人著作：(點擊以展開)

• 期刊論文
1. D. Heh, P.D. Kirsch, C.D. Young, and G. Bersuker, “A new dielectric degradation phenomenon in nMOS high-k devices under positive bias stress,” IRPS, pp. 347-351, 2008.
2. J. Huang, P.D. Kirsch, D.C. Gilmer, P. Sivasubramani, J. Price, S.H. Lee, D. Heh, C. Young, J. Oh, C.S. Park, Y. N. Tan, C. Park, P.Y. Hung, P. Lysaght, P. Majhi, H.R. Harris, G. Bersuker, K.J. Choi, B.J. Cho, H.H. Tseng, B.H. Lee, and R. Jammy, “Mechanism of High Gate Leakage Current on Surface Channel SiGe pFETs with HfSiON Dielectric and a Method to Enable sub-1nm EOT for the Gate First Process,” VLSI, pp. 82-83, 2008.
3. C.Y. Kang, C.S. Park, D. Heh, C. Young, P. Kirsch, H.B. Park, R. Choi, G. Bersuker, J.W. Yang, B.H. Lee, J. Lichtenwalner, J.S. Jur, A.I. Kingon, and R. Jammy, “Performance and reliability characteristics of the band edge high-k/metal gate nMOSFETs with La-doped Hf-silicate gate dielectrics,” IRPS, pp. 663-664, 2008.
4. D. Heh, C.D. Young, and G. Bersuker, “Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High-k Dielectrics Subjected to PBTI Stress,” IEEE Electron Device Letters, vol. 29, pp. 180-182, 2008.
5. P. Majhi, P. Kalra, R. Harris, K.J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B.J. Cho, S. Banerjee, W. Tsai, H.H. Tseng, and R. Jammy, “Demonstration of High-Performance PMOSFETs Using Si– SixGe1-x –Si Quantum Wells With High-_/Metal-Gate Stacks,” IEEE Electron Device Letters, vol. 29, pp. 99-101, 2008.
6. K.S. Min, C.Y. Kang, O.S. Yoo, B.J. Park, S.W. Kim, C.D. Young, D. Heh, G. Bersuker, B.H. Lee, and G.Y. Yeom, “Plasma induced damage of aggressively scaled gate dielectric (EOT ＜＜ 1.0nm) in metal gate/high-k dielectric CMOSFETs,” IRPS, pp. 723-724, 2008.
7. H.D. Xiong, D. Heh, S. Yang, X. Zhu, M. Gurfinkel, G. Bersuker, D.E. Ioannou, C.A. Richter, K.P. Cheung, and J.S. Suehle, “Stress-induced defect generation in HfO2/SiO2 stacks observed by using charge pumping and low frequency noise measurements,” IRPS, pp. 319-323, 2008.
8. J. Huang, P.D. Kirsch, M. Hussain, D. Heh, P. Sivasubramani, C. Young, D.C. Gilmer, C.S. Park, Y.N. Tan, C. Park, H.R. Harris, P. Majhi, G. Bersuker, B.H. Lee, H.H. Tseng, and R. Jammy, “Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs,” VLSI-TSA, pp. 152-153, 2008.
9. Y.N. Tan, H.C. Wen, C. Park, D.C. Gilmer, C.D. Young, D. Heh, P. Sivasubramani, J. Huang, P. Majhi, P.D. Kirsch, B.H. Lee, H.H. Tseng, and R. Jammy, “Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance,” VLSI-TSA, pp. 54-55, 2008.
10. J. Huang, P.D. Kirsch, D. Heh, C.Y. Kang, G. Bersuker, M. Hussain, P. Majhi, P. Sivasubramani, D.C. Gilmer, aN. Goel, M.A. Quevedo-Lopez, C. Young, C.S. Park, C. Park, P. Y. Hung, J. Price, H.R. Harris, B.H. Lee, H.H. Tseng, and R. Jammy, “Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node Application,” IEDM, 2008.
11. .Y. Kang, C.D. Young, J. Huang, P. Kirsch, D. Heh, P. Sivasubramani, H. K. Park, G, Bersuker, B. H. Lee, H.S. Choi1, K.T. Lee1, Y-H. Jeong1, J. Lichtenwalner, A. I. Kingon, H.H. Tseng and R. Jammy, “The Impact of La-doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs under Various Gate Stress Conditions,” IEDM, 2008.
12. G. Bersuker, D. Heh, C. Young, H. Park, P. Khanal, L. Larcher1, A. Padovani, P. Lenahan, J. Ryan, B.H. Lee, H. Tseng, and R. Jammy, “Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric,” IEDM, 2008.
13. N. Goela, D. Heh, S. Koveshnikova, I. Ok, S. Oktyabrskyc, V. Tokranovc, R. Kambhampatic, M.Yakimovc, Y. Sund, P. Pianettad, C.K. Gaspee, M.B. Santose, J. Leef, S. Dattag, P. Majhia, and W. Tsaia, “Addressing The Gate Stack Challenge For High Mobility InxGa1-xAs Channels For NFETs,” IEDM, 2008.
14. C.Y. Kang, P.D. Kirsch, D. Heh, C.D. Young, P. Sivasubramani, G. Bersuker, S.C. Song, R. Choi, B.H. Lee, D.J. Lichtenwalner, J. S. Jur, A.I. Kingon, and R. Jammy, “NMOSFET Reliability Improvement attributed to the Interfacial Dipole formed by La Incorporation in HfO2,” SSDM, 2008
15. H. Park, G. Bersuer, N. Goel, D. Gilmer, D. Heh, C.Y. Kang, H.H. Tseng, P.D. Kirsch, and R. Jammy, “Degradation behavior of TANOS memory devices in retention mode,” NVMTS, 2008.
16. D. Heh, P.D. Kirsch, C.D. Young, C.Y. Kang, and G. Bersuker, “New Defect generation in Nitrogen Contented nMOS High-k Devices,” in Integrated Reliability Workshop final report, pp. 103-106, 2007
17. . Heh, C.D. Young, R. Choi, and G. Bersuker, “Extraction of the Threshold-voltage Shift by the Single-Pulse Technique,” IEEE Electron Device Letters, vol. 28, pp. 734-736, 2007.
18. D. Heh, R. Choi, and G. Bersuker, “Comparison of On-The-Fly and Single Pulse Methods for Evaluating Threshold Voltage Instability in High-k NMOSFETs,” IEEE Electron Device Letters, vol. 28, pp. 245-247, 2007.
19. D. Heh, “Overview of Electrical Characterization and Reliability on MOSFET,” Invited talk, National Tsing-Hua University, Hsinchu Taiwan 2007.
20. D. Heh, C.D. Young, G.A. Brown, P.Y. Hung, A. Diebold, E.M. Vogel, J.B. Bernstein, and G. Bersuker, “Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack,” IEEE Trans. Electron Devices, vol. 54, pp. 1338-1445, 2007.
21. H.D. Xiong, D. Heh, M. Gurfinkel, Q.Li, Y. Shapira, C. Richter, G. Bersuker, R. Choi, and J.S. Suehle, “Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise and charge pumping measurements,”, Microelectronic Engineering, vol 84, pp. 2230-2234,2007.
22. S. Joshi, C. Krug, D. Heh, H.J. Na, H.R. Harris, J.W. Oh, P.D. Kirsch, P. Majhi, B.H. Lee, H.H. Tseng, R. Jammy, J.C. Lee, and S.K. Banerjee, “Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack,” IEEE Electron Device Letters, vol. 28, pp. 308-311, 2007.
23. . Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra, and R. Choi, “Progressive Breakdown Characteristics of High-K/Metal Gate Stacks,” IRPS, pp. 49-54, 2007.
24. P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R. Harris, P. Kirsch, R. Choi, M.Chang, J. Lee, H. Hwang, H.H. Tseng, R. Jammy, and T.K. Liu, “Impact of Flash Annealing on Performance and Reliability of High-y/Metal-Gate MOSFETs for sub-45nm CMOS,” IEDM, pp. 353-356, 2007.
25. S. Suthram, P. Majhi, G. Sun, P. Kalra, H.R. Harris, K.J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B.J. Cho, M.M. Hussain, C. Smith, S. Banerjee, W. Tsai, S.E. Thompson, H.H. Tseng, and R. Jammy, “High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node,” IEDM, pp. 727-730, 2007.
26. . Choi, C. Young, C.Y. Kang; D. Heh, G. Bersuker, S. Krishnan; P.D. Kirsch, A. Neugroschel, S.C. Song, B.H. Lee, and R. Jammy, “Reliability Assessment on Highly Manufacturable MOSFETs with Metal Gate and Hf based Gate Dielectrics,” IPFA, pp. 26-29, 2007.
27. K.T. Lee, J. Schmitz, G.A. Brown, D. Heh, R. Choi, R. Harris, S.C. Song, B.H. Lee, I.S. Han, H.D. Lee, and Y.H. Jeong, “Test Structures for Accurate UHF C-V Measurements of Nano-Scale CMOSFETs with HfSiON and TiN Metal Gate,” ICMTS, pp. 124-127, 2007.
28. H.D. Xiong, D. Heh, Moshe Gurfinkel, Qiliang Li, Yoram Shapira, C. Richter, Gennadi Bersuker, Rino Choi, and J.S. Suehle, “Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise, charge pumping measurements,” INFOS, 2007
29. D. Heh, R. Choi, C. D. Young, B. H. Lee, G. Bersuker, “A Novel Bias Temperature Instability Characterization Methodology for High-k nMOSFETs,” IEEE Electron Device Letters, vol. 27, pp. 849-851, 2006.
30. D. Heh, E.M. Vogel, J.B. Bernstein, C.D. Young, G.A. Brown, P.Y. Hung, A. Diebold, and G. Bersuker, “Spatial distributions of trapping centers in HfO2/SiO2 gate stacks,” APL., vol. 88, p. 152907, 2006.
31. D. Heh, Rino Choi, Chadwin D. Young, and Gennadi Bersuker, “Fast and slow charge trapping/detrapping processes in high-k nMOSFETs,” in Integrated Reliability Workshop final report, pp. 120-124, 2006.
32. D. Heh, Rino Choi, Chadwin D. Young, Byoung Hun Lee, and Gennadi Bersuker, “A novel bias temperature instability characterization methodology for high-k MOSFETs,” European Solid-State Device Research Conference, pp. 387-390, 2006.
33. C. D. Young, D. Heh, S. V. Nadkarni, Rino Choi, J. J. Peterson, J. Barnett, Byoung Hun Lee, and G. Bersuker, “Electron trap generation in high-k gate stacks by constant voltage stress,” IEEE Trans. Device and Material Reliab., vol. 6, pp. 123-131, 2006.
34. C. D. Young, S. Nadkarni, D. Heh, H. R. Harris, R. Choi, J. J. Peterson, J. H. Sim, S. A. Krishnan, J. Barnett, E. Vogel, B. H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker, “Detection of Electron Trap Generation due to Constant Voltage Stress on High-k Gate Stacks,” IRPS, pp. 169-173, 2006.
35. C. D. Young, D. Heh, R. Choi, J. J. Peterson, J. Barnett, B. H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker, “Detection of Trap Generation in High-k Gate Stacks due to Constant Voltage Stress,” VLSI-TSA, pp. 1-2, 2006.
36. C. D. Young, Rino Choi, D. Heh, A. Neugroschel, Hokyung Park, Chang Yong Kang, G. A. Brown, Seung Chul Song, Byoung Hun Lee, and G. Bersuker, “Assessment of Process-Induced Damage in High-κ Transistors,” ICICDT, pp. 1-4, 2006.
37. D. Heh, Chadwin D. Young, Rino Choi, and Gennadi Bersuker, “Extraction of the Threshold Voltage Shift by the Single Pulse Technique,” IEEE Electron Device Letters, vol. 28, 734-736, 2006.
38. C.Y. Kang, R. Choi, S.C. Song, K. Choi, B.S. Ju, M.M. Hussain, B.H. Lee, G. Bersuker, C. Young, D. Heh, P. Kirsch, J. Barnet, J.W. Yang, W. Xiong, H.H. Tseng, and R. Jammy, “A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si 110 Channel for Both N and PMOSFETs,” IEDM, pp. 1-4, 2006.
39. . Choi, D. Heh, C.Y. Kang, C. Young, G. Bersuker, and B.H. Lee, “Comparison of novel BTI measurements for high-k dielectric MOSFETs,” ICICDT, pp. 1117-1118, 2006.
40. A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C.Y. Kang, B.H. Lee, and R. Jammy, “An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks,” IEDM, pp. 1-4, 2006.
41. H.R. Harris, H. Alshareef, H.C. Wen, S. Krishnan, K. Choi, H. Luan, D. Heh, C.S. Park, H.B. Park, M. Hussain, B.S. Ju, P.D. Kirsch, S.C. Song, P. Majhi, B.H. Lee, and R. Jammy, “Simplified manufacturable band edge metal gate solution for NMOS without a capping layer,” IEDM, pp. 1-4, 2006.
42. E. M. Vogel, D. Heh, “Characterization of electrically active defects in high-k gate dielectrics using charge pumping,” in NATO Advanced Research Workshop on Defects in Advanced High-k Dielectric Nanoelectronic Semiconductor Devices, pp. 85-96, 2005
43. C.D. Young, D. Heh, S. Nadkarni, R. Choi, J.J. Peterson, H.R. Harris, J.H. Sim, S.A. Krishnan, J. Barnett, E.M. Vogel, B.H. Lee, P. Zeitzoff, G.A. Brown, and G. Bersuker, “Detection of trap generation in high-k gate stacks,” in Integrated Reliability Workshop final report, pp. 79-83, 2005.
44. D. Heh and E.M. Vogel, “Depth profiles of electrically active defects in high-k gate stacks using charge pumping,” Advanced Gate Stack Engineering working Group Biannual Meeting, Austin Texas, 2005.
45. D. Heh, E.M. Vogel, and Bernstein, “New insights into threshold voltage shifts for ultrathin gate oxides [MOSFETs],” in Integrated Reliability Workshop final report, pp. 99-101, 2004.
46. J.P. Han, E.M. Vogel, E.P. Gusev, C. D'Emic, C.A. Richter, D. Heh, and J.S. Suehle, “Asymmetric energy distribution of interface traps in n- and p-MOSFETs with HfO2 gate dielectricon ultrathin SiON buffer layer,” IEEE Electron Device Letters, vol. 25, pp. 126-128, 2004.
47. J.P. Han, E.M. Vogel, E.P. Gusev, C. D'Emic, C.A. Richter, D. Heh, and J.S. Suehle, “Energy distribution of interface traps in high-k gated MOSFETs,” VLSI, pp. 161-162, 2003.
48. D. Heh, E. M. Vogel, and J. B. Bernstein, ‘Impact of Substrate Hot Hole Injection on Ultra-thin Silicon Dioxide Breakdown,’ Applied Physics Letters, vol. 82, pp. 3242-3244, 2003.
49. D. Heh, E.M. Vogel, and J.B. Bernstein, “Defect generation in ultra-thin oxide over large fluence range,” in Integrated Reliability Workshop final report, pp. 9-13, 2002.
50. E.M. Vogel, D. Heh; J.B. Bernstein, and J.S. Suehle, “Impact of the trapping of anode hot holes on silicon dioxide breakdown,” IEEE Electron Device Letters, vol. 23, pp. 667-669, 2002.
51. E. M. Vogel, D. Heh, and J. B. Bernstein, ‘Interaction between low energy electrons and defects created by hot holes in ultra-thin silicon dioxide,’ Applied Physics Letters, vol. 80, pp. 3343-3345, 2002.
52. D. Heh, E.M. Vogel, and J.B. Bernstein, “Relevance of injected hot holes on the breakdown of ultra-thin silicon-dioxide metal-oxide-semiconductor devices,” American Physical Society March Meeting, Indianapolis Indiana, 2002.
53. E.M. Vogel, D. Heh, B. Wang, C.E. Weintrab, J.S. Suehle, M.D. Edelstein, and J.B. Bernstein, “Interaction of electrons with defects created by hot holes in ultra-thin silicon dioxide,” IEEE Semiconductor Interface Specialists Conference, Washington D.C., 2001.
• 會議論文
• 專書論文
• 專利
1. Time Domain Reflectometry Application in Capacitance-Voltage Measurement　（pending）